1. Field of the Invention
The present invention relates to a clock signal switching circuit.
2. Description of the Related Arts
A clock signal switching circuit is utilized in various kinds of semiconductor integrated circuit devices etc., in which the clock signal switching circuit is adapted to switch to selectively pick up one desirable clock signal out of a plurality of different clock signals generated in the semiconductor circuit.
More concretely, this kind of semiconductor integrated circuit device is provided with a clock signal source and a clock dividing circuit as well as such a clock signal switching circuit. The original clock signal is firstly generated by the clock signal source, and then, this original clock signal is divided by two, four, eight and so on, by the clock dividing circuit, so as to generate a plurality of clock signals having different cycles. The generated plurality of clock signals including the original clock signal, are then inputted to the clock signal switching circuit, so a desirable one of the clock signals is selected by the switching operation of the clock signal switching circuit, when a predetermined switching signal requesting the switching operation is given to the clock signal switching circuit.
One example according to such a related art technique is explained here with reference to FIG. 1, which shows a timing chart of the clock signal switching operation.
In FIG. 1, there are shown a clock signal CK8 and a clock signal CK1, which are assumed to be inputted to a clock signal switching circuit in a semiconductor integrated circuit device according to the above-mentioned related art technique. The clock signal CK1 is obtained by use of a dividing circuit by dividing the clock signal CK8 by eight, while the clock signal CK8 is generated by a clock signal source. On the other hand, a switching signal SL to indicate the request for the switching operation by its logical level, is inputted from the external to the clock signal switching circuit.
When the switching from the clock signal CK8 to the clock signal CK1 is to be performed at the time of T1, the logical level of the switching signal SL is turned to be high level of "1" at this time of T1, so that the clock signal switching circuit immediately performs its switching operation to select the clock signal CK1 and output it as an output clock signal CK0, as shown in FIG. 1. Further, when the switching from the clock signal CK1 to the clock signal CK8 is to be performed at the time T2, the logical level of the switching signal SL is turned to be low level of "0" at the time of T2, so that the clock signal switching circuit immediately performs its switching operation to select the clock signal CK8 and output it as the output clock signal CK0.
Accordingly, whenever it is required to change the clock signal CK0 from one to the other i.e. CK1 or CK8, the switching operation can be performed just by changing the logical level of the switching signal SL.
By the way, in a semiconductor integrated circuit device in general, it is desirable that the clock signal is always kept to be in a complete form. That is to say, it is desirable that a proper clock signal in a complete form is outputted from the clock signal switching circuit even at the moment of switching operation while the switching operation is smoothly performed.
However, in case of the above-mentioned related art circuit, when the logical level of the switching signal SL is changed, the clock switching operation is immediately performed according to the new logical level. Here, since the switching signal SL is not necessarily synchronized with the clock signal CK1 or CK8, a noise may be generated in the outputted clock signal CK0 at the time of T1 as shown in FIG. 1. Further, an improper clock signal in an incomplete form, i.e. having a shorter cycle than the real clock signal CK1, may be generated in the outputted clock signal CK0 as a result of shutting off the inputted clock signal CK1 at the time of T2 before the completion of its one cycle, as shown in FIG. 1.